Field of the Disclosure
The present disclosure relates to semiconductor technology, and more particularly, to a method for manufacturing a complementary metal oxide semiconductor (CMOS) structure.
Description of the Related Art
A CMOS structure includes metal-oxide-semiconductor field-effect transistors (MOSFETs) of two opposite types (i.e. N-type and P-type) on one semiconductor substrate. The CMOS structure is widely used in various logical circuits which operates at low power consumption. A control chip of a power converter has advantages of low power consumption, high integration level, and high speed, if being on the basis of a CMOS structure.
To complete a CMOS structure, a well region is typically formed in a semiconductor substrate for at least one type of MOSFET. Source/drain regions of the at least one type of MOSFET are then formed in the well region by ion implantation. The well region has a doping type opposite to that of the MOSFET to be formed therein, and functions as an actual semiconductor substrate of such a MOSFET. Lightly-doped drain (LDD region) regions may also be formed between the source/drain regions and a channel region for improving electric field distribution in the channel region and suppressing a short-channel effect.
In a conventional CMOS process, doping processes are usually independent of each other for different types of MOSFETs. When doped regions of one type of MOSFETs are formed, active regions of the other type of MOSFETs are blocked, or vice versa. A control chip of a power converter typically includes low-voltage MOSFETs and high-voltage MOSFETs having gate dielectrics with different thicknesses if being a CMOS structure. Well regions of the high-voltage MOSFETs are blocked when the low-voltage MOSFETs are formed, or vice versa. Consequently, a large number of masks must be used in various doping steps in the conventional CMOS process, which increases manufacturing cost, and may cause low yield and poor reliability of the product due to possible mismatching of different masks.
Thus, it is desirable to further reduce manufacturing cost of a CMOS process and reduce reliability problem due to the process complexity.